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february 15, 2007 ? cypress semiconductor 2004-2007 ? document no. 38-12018 rev. *j 1 psoc? mixed-signal array final data sheet cy8c24094, cy8c24794, cy8c24894, and CY8C24994 psoc? functional overview the psoc? family consists of many mixed-signal array with on-chip controller devices. all psoc family devices are designed to replace traditional mcus, system ics, and the numerous discrete components t hat surround them. the psoc cy8c24x94 devices are unique members of the psoc family because it includes a full-featured, full-speed (12 mbps) usb port. configurable analog, digital, and interconnect circuitry enable a high level of integratio n in a host of industrial, con- sumer, and communication applications. this architecture allows the user to create customized periph- eral configurations t hat match the requiremen ts of each individ- ual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts and packages. the psoc architecture, as illustrated on the left, is comprised of four main areas: psoc core, digital system, analog system, and system resources including a full-speed usb port. config- urable global busing allows all the device resources to be com- bined into a complete custom system. the psoc cy8c24x94 devices can have up to seven io ports that connect to the glo- bal digital and analog interconnects, providing access to 4 digi- tal blocks and 6 analog blocks. features cy8c24894 includes an xres pin to support in-system seri al programming (issp) a nd external reset control powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? two 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 to 5.25v operating voltage ? industrial temperature range: -40c to +85c ? usb temperature range: -10c to +85c advanced peripherals (psoc blocks) ? 6 rail-to-rail analog psoc blocks provide: - up to 14-bit adcs - up to 9-bit dacs - programmable gain amplifiers - programmable filters and comparators ? 4 digital psoc blocks provide: - 8- to 32-bit timers, counters, and pwms - crc and prs modules - full-duplex uart - multiple spi ? masters or slaves - connectable to all gpio pins ? complex peripherals by combining blocks ? capacitive sensing application capability full-speed usb (12 mbps) ? four uni-directional endpoints ? one bi-directional control endpoint ? usb 2.0 compliant ? dedicated 256 byte buffer ? no external crystal required flexible on-chip memory ? 16k flash program storage 50,000 erase/ write cycles ? 1k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 48 analog inputs on gpio ? two 33 ma analog outputs on gpio ? configurable interrupt on all gpio precision, programmable clocking ? internal 4% 24/48 mhz oscillator ? internal oscillator for watchdog and sleep ? .25% accuracy for usb with no external components additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory digital system sram 1k inte rrup t controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. port 5 port 4 port 3 port 2 port 1 port 0 analog drivers analog block array inte rnal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c usb port 7 s y s t e m b u s analog input muxing [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 2 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview the psoc core the psoc core is a powerful engine that supports a rich fea- ture set. the core includes a cpu, memory, clocks, and config- urable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- processor. the cpu utilizes an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 16k of flash for program storage, 1k of sram for data storage, and up to 2k of eeprom emulated using the flash. program flash uti lizes four protection levels on blocks of 64 bytes, allowing cu stomized software ip protection. the psoc device incorporates flexible internal clock genera- tors, including a 24 mhz imo (internal main oscillator) accurate to 8% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. the clocks, together with program- mable clock dividers (as a system resource), provide the flexi- bility to integrate almost any timing requirement into the psoc device. in usb systems, the imo will self-tune to 0.25% accu- racy for usb communication. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfac- ing. every pin also has the capa bility to generat e a system inter- rupt on high level, low leve l, and change from last read. the digital system the digital system is composed of 4 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peri pherals, which are called user module references. digital system block diagram digital peripheral configurations include those listed below. full-speed usb (12 mbps) pwms (8 to 32 bit) pwms with dead band (8 to 24 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master cyclical redundancy checker/generator (8 to 32 bit) irda pseudo random sequence generators (8 to 32 bit) the digital blocks can be conne cted to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability fr ees your designs from the con- straints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device fa mily. this allows you the opti- mum choice of system resources for your application. family resources are shown in the table titled psoc device character- istics. the analog system the analog system is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support sp ecific application requirements. some of the more common psoc analog functions (most avail- able as user modules) are listed below. analog-to-digital converters (up to 2, with 6- to 14-bit resolu- tion, selectable as incremental, delta sigma, and sar) filters (2 and 4 pole band-pass, low-pass, and notch) amplifiers (up to 2, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to 2, with 16 selectable thresholds) dacs (up to 2, with 6- to 9-bit resolution) multiplying dacs (up to 2, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a psoc core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7 [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 3 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview analog blocks are arranged in a column of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as s hown in the figure below. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin in ports 0- 5. pins can be connected to the bus individually or in any com- bination. the bus also connects to the analog system for analy- sis with comparators and analog-to-digital converters. it can be split into two sections for simultaneous dual-channel process- ing. an additional 8:1 analog input multiplexer provides a sec- ond path to bring port 0 pins to the analog array. switch control logic enables sele cted pins to precharge continu- ously under hardware control. this enables capacitive mea- surement for applications su ch as touch sensing. other multiplexer applications include: track pad, finger sensing. chip-wide mux that allows analog input from up to 48 io pins. crosspoint connection between any io pin combinations. when designing capacitive sensing applications, refer to the lat- est signal-to-noise signal level requirements application notes, which can be found under http://www.cypress.com >> design resources >> application notes. in general, and unless oth- erwise noted in the relevant application notes, the minimum signal-to-noise ratio (snr) for capsense applications is 5:1. additional system resources system resources, provide additi onal capability useful to com- plete systems. additional resources include a multiplier, deci- mator, low voltage detection, and power on reset. brief statements describing the merits of each resource follow. full-speed usb (12 mbps) with 5 configurable endpoints and 256 bytes of ram. no external components required except two series resistors. wider than commercial temperature usb operation (-10c to +85c). digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. two multiply accumulates (macs) provide fast 8-bit multipli- ers with 32-bit accumulate, to assist in both general math as well as digital filters. decimator provides a custom hardware filter for digital signal processing apps. including creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, multi-master are supported. low voltage detection (lvd) interrupts signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates th e need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, including adcs and dacs. versatile analog multiplexer system. acb00 acb01 block array array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference all io (except port 7) analog mux bus [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 4 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. the following table lists the resources available for specific psoc dev ice groups. the device covered by this data sheet is shown in the highlighted row of the table getting started the quickest path to understandi ng the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circ uit and presents specific pin, register, and electrical specif ications. for in-depth information, along with detailed programming information, reference the psoc mixed-signal array technical reference manual . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com/psoc. to determine which psoc device meets your requirements, navigate through the psoc decision tree in the application note an2209 at http://www.cypress.com and select application notes under the design resources. development kits development kits are available fr om the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com, click the online store shopping cart icon at the bottom of the web page, and click psoc (program- mable system-on-chip) to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog and capsense. go to http:// www.cypress.com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com, click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are listed by date as default. psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2k 32k cy8c27x43 up to 44 28124412 256 bytes 16k cy8c24x94 56 1 4 48 2 2 6 1k 16k cy8c24x23a up to 24 1412226 256 bytes 4k cy8c21x34 up to 28 142802 4 a a. limited analog functionality . 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 a 256 bytes 4k cy8c20x34 up to 28 0 0 28 0 0 3 b b. two analog blocks and one capsense. 512 bytes 8k [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 5 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (reference the psoc designer func- tional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write a pplication code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc designer [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 6 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reco nfiguration. dynamic configu- ration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurat ions and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configur ation, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the us er can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured design s to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan contro ller, and magnetic card reader. application editor in the application editor yo u can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c co de. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the psoc family of devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context- sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 7 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digita l hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. each block has severa l registers that determine its function and connectivity to other blocks, multiplexers, buses and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware pe ripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library con- tains over 50 common peripherals such as adcs, dacs tim- ers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precis e configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digi tal psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service rou- tines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificat ions. each data sheet describes the use of each user module parameter and documents the set- ting of each register cont rolled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. yo u pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate applicati on? step. this causes psoc designer to generate source co de that automatically configures the device to your specification and provides the high-level user module api functions. user module/source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s ap plication editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the hex image to the in- circuit emulator (ice) where it runs at full speed. de bugger capabilities rival those of systems costing many times more. in addit ion to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 8 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet psoc? overview document conventions acronyms used the following table lists the acrony ms that are used in this doc- ument. units of measure a units of measure table is loca ted in the electrical specifica- tions section. table 3-1 on page 22 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding conven tion. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed-signal array technical refer- ence manual . this document encompasses and is organized into the following chapters and sections. 1. pin information ........................................................................................ 9 1.1 56-pin part pinout ......................................................................... 9 1.2 56-pin part pinout (with xres) .................................................. 10 1.3 68-pin part pinout ........................................................................ 11 1.4 68-pin part pinout (on-chip debug) ........................................... 12 1.5 100-ball vfbga part pinout ........................................................ 13 1.6 100-ball vfbga part pinout (on-chip debug) ........................... 15 1.7 100-pin part pinout (on-chip debug) .......................................... 17 2. register reference ................................................................................ 19 2.1 register conventions ................................................................... 19 2.1.1 abbreviations used ....................................................... 19 2.2 register mapping tables ............................................................. 19 3. electrical specifications ....................................................................... 22 3.1 absolute maximum ratings ......................................................... 23 3.2 operating temperature ................................................................ 23 3.3 dc electrical characteristics ........................................................ 23 3.3.1 dc chip-level specifications ........................................ 23 3.3.2 dc general purpose io specifications ......................... 24 3.3.3 dc full-speed usb specifications ............................... 24 3.3.4 dc operational amplifier specifications ....................... 25 3.3.5 dc low power comparator specifications ................... 26 3.3.6 dc analog output buffer specifications ....................... 27 3.3.7 dc analog reference specifications ............................ 28 3.3.8 dc analog psoc block specifications .......................... 29 3.3.9 dc por and lvd specifications .................................. 29 3.3.10 dc programming specifications ................................... 30 3.4 ac electrical characteristics ........................................................ 31 3.4.1 ac chip-level specifications ........................................ 31 3.4.2 ac general purpose io specifications ......................... 32 3.4.3 ac full-speed usb specifications ............................... 32 3.4.4 ac operational amplifier specifications ........................ 33 3.4.5 ac low power comparator specifications ................... 35 3.4.6 ac digital block specifications ..................................... 35 3.4.7 ac external clock specifications .................................. 35 3.4.8 ac analog output buffer specifications ........................ 36 3.4.9 ac programming specifications .................................... 37 3.4.10 ac i2c specifications .................................................... 38 4. packaging information .......................................................................... 39 4.1 packaging dimensions ................................................................. 39 4.2 thermal impedance ..................................................................... 42 4.3 solder reflow peak temperature ................................................ 42 5. development tool selection ................................................................ 43 5.1 software ....................................................................................... 43 5.1.1 psoc designer .............................................................. 43 5.1.2 psoc express ............................................................... 43 5.1.3 psoc programmer ........................................................ 43 5.1.4 cy3202-c imagecraft c compiler ............................... 43 5.2 development kits ......................................................................... 43 5.2.1 cy3215-dk basic development kit .............................. 43 5.2.2 cy3210-expressdk development kit ........................... 44 5.3 evaluation tools ........................................................................... 44 5.3.1 cy3210-miniprog1 ........................................................ 44 5.3.2 cy3210-psoceval1 ...................................................... 44 5.3.3 cy3214-psocevalusb ................................................ 44 5.4 device programmers ................................................................... 44 5.4.1 cy3216 modular programmer ...................................... 44 5.4.2 cy3207issp in-system serial programmer (issp) ..... 44 5.5 accessories (emulation and programming) ................................. 45 5.6 3rd-party tools ............................................................................. 45 5.7 build a psoc emulator into your board ...................................... 45 6. ordering information ............................................................................ 46 6.1 ordering code definitions ............................................................ 46 7. sales and company information ......................................................... 47 7.1 revision history ........................................................................... 47 7.2 copyrights and code protection .................................................. 48 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor sram static random access memory [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 9 1. pin information this chapter describes, lists, and illu strates the cy8c24x94 psoc device fam ily pins and pinout configuration. the cy8c24x94 psoc devices are available in the following packages , all of which are shown on the following pages. every port p in (labeled with a ?p?) is capable of digital io. however, vss, vdd, and xres are not capable of digital io. 1.1 56-pin part pinout table 1-1. 56-pin part pinout (qfn ** ) see legend details and footnotes in table 1-2 on page 10 . pin no. type name description cy8c24794 56-pin psoc device digital analog 1 io i, m p2[3] direct switched capacitor block input. 2 io i, m p2[1] direct switched capacitor block input. 3 io m p4[7] 4 io m p4[5] 5 io m p4[3] 6 io m p4[1] 7 io m p3[7] 8 io m p3[5] 9 io m p3[3] 10 io m p3[1] 11 io m p5[7] 12 io m p5[5] 13 io m p5[3] 14 io m p5[1] 15 io m p1[7] i2c serial clock (scl). 16 io m p1[5] i2c serial data (sda). 17 io m p1[3] 18 io m p1[1] i2c serial clock (scl), issp sclk*. 19 power vss ground connection. 20 usb d+ 21 usb d- 22 power vdd supply voltage. 23 io p7[7] 24 io p7[0] 25 io m p1[0] i2c serial data (sda), issp sdata*. 26 io m p1[2] 27 io m p1[4] 28 io m p1[6] 29 io m p5[0] pin no. type name description 30 io m p5[2] digital analog 31 io m p5[4] 44 io m p2[6] external voltage reference (vref) input. 32 io m p5[6] 45 io i, m p0[0] analog column mux input. 33 io m p3[0] 46 io i, m p0[2] analog column mux input. 34 io m p3[2] 47 io i, m p0[4] analog column mux input vref. 35 io m p3[4] 48 io i, m p0[6] analog column mux input. 36 io m p3[6] 49 power vdd supply voltage. 37 io m p4[0] 50 power vss ground connection. 38 io m p4[2] 51 io i, m p0[7] analog column mux input,. 39 io m p4[4] 52 io io, m p0[5] analog column mux input and column output. 40 io m p4[6] 53 io io, m p0[3] analog column mux input and column output. 41 io i, m p2[0] direct switched capacitor block input. 54 io i, m p0[1] analog column mux input. 42 io i, m p2[2] direct switched capacitor block input. 55 io m p2[7] 43 io m p2[4] external analog ground (agnd) input. 56 io m p2[5] qfn (top view ) a, i, m, p2[3] a, i, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29 [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 10 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.2 56-pin part pinout (with xres) table 1-2. 56-pin part pinout (qfn ** ) pin no. type name description cy8c24894 56-pin psoc device digital analog 1 io i, m p2[3] direct switched capacitor block input. 2 io i, m p2[1] direct switched capacitor block input. 3 io m p4[7] 4 io m p4[5] 5 io m p4[3] 6 io m p4[1] 7 io m p3[7] 8 io m p3[5] 9 io m p3[3] 10 io m p3[1] 11 io m p5[7] 12 io m p5[5] 13 io m p5[3] 14 io m p5[1] 15 io m p1[7] i2c serial clock (scl). 16 io m p1[5] i2c serial data (sda). 17 io m p1[3] 18 io m p1[1] i2c serial clock (scl), issp sclk*. 19 power vss ground connection. 20 usb d+ 21 usb d- 22 power vdd supply voltage. 23 io p7[7] 24 io p7[0] 25 io m p1[0] i2c serial data (sda), issp sdata*. 26 io m p1[2] 27 io m p1[4] 28 io m p1[6] 29 io m p5[0] pin no. type name description 30 io m p5[2] digital analog 31 io m p5[4] 44 io m p2[6] external voltage reference (vref) input. 32 io m p5[6] 45 io i, m p0[0] analog column mux input. 33 io m p3[0] 46 io i, m p0[2] analog column mux input. 34 io m p3[2] 47 io i, m p0[4] analog column mux input vref. 35 io m p3[4] 48 io i, m p0[6] analog column mux input. 36 input xres active high external reset with internal pull down. 49 power vdd supply voltage. 37 io m p4[0] 50 power vss ground connection. 38 io m p4[2] 51 io i, m p0[7] analog column mux input,. 39 io m p4[4] 52 io io, m p0[5] analog column mux input and column output. 40 io m p4[6] 53 io io, m p0[3] analog column mux input and column output. 41 io i, m p2[0] direct switched capacitor block input. 54 io i, m p0[1] analog column mux input. 42 io i, m p2[2] direct switched capacitor block input. 55 io m p2[7] 43 io m p2[4] external analog ground (agnd) input. 56 io m p2[5] legend a = analog, i = input, o = output, and m = analog mux input. * these are the issp pins, which are not high z at por. see the psoc mixed-signal array technical reference manual for details. ** the center pad on the qfn package should be connected to groun d (vss) for best mechanical, thermal, and electrical performan ce. if not connected to ground, it should be electrically floa ted and not connected to any other signal. qfn (top view) a, i, m, p2[3] a, i, m, p2[1] m, p4 [7 ] m, p4 [5 ] m, p4 [3 ] m, p4 [1 ] m, p3 [7 ] m, p3 [5 ] m, p3 [3 ] m, p3 [1 ] m, p5 [7 ] m, p5 [5 ] m, p5 [3 ] m, p5 [1 ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m xr es p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29 [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 11 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.3 68-pin part pinout the 68-pin qfn part table and drawing below is for the CY8C24994 psoc device. table 1-3. 68-pin part pinout (qfn**) pin no. type name description CY8C24994 68-pin psoc device digital analog 1 io m p4[7] 2 io m p4[5] 3 io m p4[3] 4 io m p4[1] 5 nc no connection. 6 nc no connection. 7 power vss ground connection. 8 io m p3[7] 9 io m p3[5] 10 io m p3[3] 11 io m p3[1] 12 io m p5[7] 13 io m p5[5] 14 io m p5[3] 15 io m p5[1] 16 io m p1[7] i2c serial clock (scl). 17 io m p1[5] i2c serial data (sda). 18 io m p1[3] 19 io m p1[1] i2c serial clock (scl) issp sclk*. 20 power vss ground connection. 21 usb d+ 22 usb d- 23 power vdd supply voltage. 24 io p7[7] 25 io p7[6] 26 io p7[5] 27 io p7[4] 28 io p7[3] 29 io p7[2] pin no. type name description 30 io p7[1] digital analog 31 io p7[0] 50 io m p4[6] 32 io m p1[0] i2c serial data (sda), issp sdata*. 51 io i,m p2[0] direct switched capacitor block input. 33 io m p1[2] 52 io i,m p2[2] direct switched capacitor block input. 34 io m p1[4] optional external clock input (ext- clk). 53 io m p2[4] external analog ground (agnd) input. 35 io m p1[6] 54 io m p2[6] external voltage reference (vref) input. 36 io m p5[0] 55 io i,m p0[0] analog column mux input. 37 io m p5[2] 56 io i,m p0[2] analog column mux input and column output. 38 io m p5[4] 57 io i,m p0[4] analog column mux input and column output. 39 io m p5[6] 58 io i,m p0[6] analog column mux input. 40 io m p3[0] 59 power vdd supply voltage. 41 io m p3[2] 60 power vss ground connection. 42 io m p3[4] 61 io i,m p0[7] analog column mux input, integration input #1 43 io m p3[6] 62 io io,m p0[5] analog column mux input and column output, integra- tion input #2. 44 nc no connection. 63 io io,m p0[3] analog column mux input and column output. 45 nc no connection. 64 io i,m p0[1] analog column mux input. 46 input xres active high pin reset with internal pull down. 65 io m p2[7] 47 io m p4[0] 66 io m p2[5] 48 io m p4[2] 67 io i,m p2[3] direct switched capacitor block input. 49 io m p4[4] 68 io i,m p2[1] direct switched capacitor block input. legend a = analog, i = input, o = output, nc = no connection, m = analog mux input. * these are the issp pins, which are not high z at por. see the psoc mixed-signal array technical reference manual for details. ** the center pad on the qfn package should be connected to groun d (vss) for best mechanical, thermal, and electrical performan ce. if not connected to ground, it should be electrically floa ted and not connected to any other signal. m, p4 [7 ] m, p4 [5 ] m, p4 [3 ] m, p4 [1 ] nc nc vs s m, p3 [7 ] m, p3 [5 ] m, p3 [3 ] m, p3 [1 ] m, p5 [7 ] m, p5 [5 ] m, p5 [3 ] m, p5 [1 ] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] p7[5] i2c sda, m, p1[0] i2c scl, m, p1[1] vss d + d - vdd p7[7] p7[6] p7[4] p7[3] p7[2] p7[1] p7[0] m, p1[2] m, p1[4] p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xr es nc nc p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m p2[1], m, ai p2[3], m, ai p2[5], m p2[7], m p0[1], m, ai p0[3], m, aio p0[5], m, aio p0[7], m, ai vss vdd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai p2[6], m, ext. vref p2[4], m, ext. agnd p2[2], m, ai 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 12 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.4 68-pin part pinout (on-chip debug) the 68-pin qfn part table and drawing below is for the cy8c24094 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production. table 1-4. 68-pin part pinout (qfn**) pin no. type name description cy8c24094 68-pin ocd psoc device digital analog 1 io m p4[7] 2 io m p4[5] 3 io m p4[3] 4 io m p4[1] 5 ocde ocd even data io. 6 ocdo ocd odd data output. 7 power vss ground connection. 8 io m p3[7] 9 io m p3[5] 10 io m p3[3] 11 io m p3[1] 12 io m p5[7] 13 io m p5[5] 14 io m p5[3] 15 io m p5[1] 16 io m p1[7] i2c serial clock (scl). 17 io m p1[5] i2c serial data (sda). 18 io m p1[3] 19 io m p1[1] i2c serial clock (scl), issp sclk*. 20 power vss ground connection. 21 usb d+ 22 usb d- 23 power vdd supply voltage. 24 io p7[7] 25 io p7[6] 26 io p7[5] 27 io p7[4] 28 io p7[3] 29 io p7[2] pin no. type name description 30 io p7[1] digital analog 31 io p7[0] 50 io m p4[6] 32 io m p1[0] i2c serial data (sda), issp sdata*. 51 io i,m p2[0] direct switched capacitor block input. 33 io m p1[2] 52 io i,m p2[2] direct switched capacitor block input. 34 io m p1[4] optional external clock input (ext- clk). 53 io m p2[4] external analog ground (agnd) input. 35 io m p1[6] 54 io m p2[6] external voltage reference (vref) input. 36 io m p5[0] 55 io i,m p0[0] analog column mux input. 37 io m p5[2] 56 io i,m p0[2] analog column mux input and column output. 38 io m p5[4] 57 io i,m p0[4] analog column mux input and column output. 39 io m p5[6] 58 io i,m p0[6] analog column mux input. 40 io m p3[0] 59 power vdd supply voltage. 41 io m p3[2] 60 power vss ground connection. 42 io m p3[4] 61 io i,m p0[7] analog column mux input, integration input #1 43 io m p3[6] 62 io io,m p0[5] analog column mux input and column output, integra- tion input #2. 44 hclk ocd high-speed clock output. 63 io io,m p0[3] analog column mux input and column output. 45 cclk ocd cpu clock output. 64 io i,m p0[1] analog column mux input. 46 input xres active high pin reset with internal pull down. 65 io m p2[7] 47 io m p4[0] 66 io m p2[5] 48 io m p4[2] 67 io i,m p2[3] direct switched capacitor block input. 49 io m p4[4] 68 io i,m p2[1] direct switched capacitor block input. legend a = analog, i = input, o = output, m = analog mux input, ocd = on-chip debugger. * these are the issp pins, which are not high z at por. see the psoc mixed-signal array technical reference manual for details. ** the center pad on the qfn package should be connected to groun d (vss) for best mechanical, thermal, and electrical performan ce. if not connected to ground, it should be electrically floa ted and not connected to any other signal. m, p4[7] m, p4[5] m, p4[3] m, p4[1] ocde ocdo vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] p7[5] i2c sda, m, p1[0] i2c scl, m, p1[1] vss d + d - vdd p7[7] p7[6] p7[4] p7[3] p7[2] p7[1] p7[0] m, p1[2] m, p1[4] p2[0], m, ai p4[6], m p4[4], m p4[2], m p4[0], m xres cclk hclk p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m p2[1], m, ai p2[3], m, ai p2[5], m p2[7], m p0[1], m, ai p0[3], m, aio p0[5], m, aio p0[7], m, ai vss vdd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai p2[6], m, ext. vref p2[4], m, ext. agnd p2[2], m, ai 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 13 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.5 100-ball vfbga part pinout the 100-ball vfbga part is for the CY8C24994 psoc device. table 1-5. 100-ball part pinout (vfbga) pin no. digital analog name description pin no. digital analog name description a1 power vss ground connection. f1 nc no connection. a2 power vss ground connection. f2 io m p5[7] a3 nc no connection. f3 io mp3[5] a4 nc no connection. f4 io mp5[1] a5 nc no connection. f5 power vss ground connection. a6 power vdd supply voltage. f6 power vss ground connection. a7 nc no connection. f7 io mp5[0] a8 nc no connection. f8 io mp3[0] a9 power vss ground connection. f9 xres active high pin reset with internal pull down. a10 power vss ground connection. f10 io p7[1] b1 power vss ground connection. g1 nc no connection. b2 power vss ground connection. g2 io m p5[5] b3 io i,m p2[1] direct switched capacitor block input. g3 io mp3[3] b4 io i,m p0[1] analog column mux input. g4 io m p1[7] i2c serial clock (scl). b5 io i,m p0[7] analog column mux input. g5 io m p1[1] i2c serial clock (scl), issp sclk*. b6 power vdd supply voltage. g6 io m p1[0] i2c serial data (sda), issp sdata*. b7 io i,m p0[2] analog column mux input. g7 io mp1[6] b8 io i,m p2[2] direct switched capacitor block input. g8 io m p3[4] b9 power vss ground connection. g9 io m p5[6] b10 power vss ground connection. g10 io p7[2] c1 nc no connection. h1 nc no connection. c2 io m p4[1] h2 io mp5[3] c3 io m p4[7] h3 io mp3[1] c4 io m p2[7] h4 io m p1[5] i2c serial data (sda). c5 io io,m p0[5] analog column mux input and column output. h5 io m p1[3] c6 io i,m p0[6] analog column mux input. h6 io m p1[2] c7 io i,m p0[0] analog column mux input. h7 io mp1[4] c8 io i,m p2[0] direct switched capacitor block input. h8 io mp3[2] c9 io m p4[2] h9 io m p5[4] c10 nc no connection. h10 io p7[3] d1 nc no connection. j1 power vss ground connection. d2 io m p3[7] j2 power vss ground connection. d3 io m p4[5] j3 usb d+ d4 io m p2[5] j4 usb d- d5 io io,m p0[3] analog column mux input and column output. j5 power vdd supply voltage. d6 io i,m p0[4] analog column mux input. j6 io p7[7] d7 io m p2[6] external voltage reference (vref) input. j7 io p7[0] d8 io m p4[6] j8 io mp5[2] d9 io m p4[0] j9 power vss ground connection. d10 nc no connection. j10 power vss ground connection. e1 nc no connection. k1 power vss ground connection. e2 nc no connection. k2 power vss ground connection. e3 io m p4[3] k3 nc no connection. e4 io i,m p2[3] direct switched capacitor block input. k4 nc no connection. e5 power vss ground connection. k5 power vdd supply voltage. e6 power vss ground connection. k6 io p7[6] e7 io m p2[4] external analog ground (agnd) input. k7 io p7[5] e8 io m p4[4] k8 io p7[4] e9 io m p3[6] k9 power vss ground connection. e10 nc no connection. k10 power vss ground connection. legend a = analog, i = input, o = output, m = analog mux input, nc = no connection. * this is the issp pin, which is not high z at por. see the psoc mixed-signal array technical reference manual for details. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 14 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information CY8C24994 vss vss nc nc nc vdd nc nc vss vss vss vss p2[1] p0[1] p0[7] vdd p0[2] p2[2] vss vss nc p4[1] p4[7] p2[7] p0[5] p0[6] p0[0] p2[0] p4[2] nc nc p3[7] p4[5] p2[5] p0[3] p0[4] p2[6] p4[6] p4[0] nc nc nc p4[3] p2[3] vss vss p2[4] p4[4] p3[6] nc nc p5[7] p3[5] p5[1] vss vss p5[0] p3[0] xres p7[1] nc p5[5] p3[3] p1[7] p1[1] p1[0] p1[6] p3[4] p5[6] p7[2] nc p5[3] p3[1] p1[5] p1[3] p1[2] p1[4] p3[2] p5[4] p7[3] vss vss d + d - vdd p7[7] p7[0] p5[2] vss vss vss vss nc nc vdd p7[6] p7[5] p7[4] vss vss 12345678910 a b c d e f g h j k bga (top view) [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 15 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.6 100-ball vfbga part pi nout (on-chip debug) the 100-pin vfbga part table and drawing below is for the cy8c24094 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debu gging. it is not available for production. table 1-6. 100-ball part pinout (vfbga) pin no. digital analog name description pin no. digital analog name description a1 power vss ground connection. f1 ocde ocd even data io. a2 power vss ground connection. f2 io m p5[7] a3 nc no connection. f3 io m p3[5] a4 nc no connection. f4 io m p5[1] a5 nc no connection. f5 power vss ground connection. a6 power vdd supply voltage. f6 power vss ground connection. a7 nc no connection. f7 io m p5[0] a8 nc no connection. f8 io m p3[0] a9 power vss ground connection. f9 xres active high pin reset with internal pull down. a10 power vss ground connection. f10 io p7[1] b1 power vss ground connection. g1 ocdo ocd odd data output. b2 power vss ground connection. g2 io m p5[5] b3 io i,m p2[1] direct switched capacitor block input. g3 io m p3[3] b4 io i,m p0[1] analog column mux input. g4 io m p1[7] i2c serial clock (scl). b5 io i,m p0[7] analog column mux input. g5 io m p1[1] i2c serial clock (scl), issp sclk*. b6 power vdd supply voltage. g6 io m p1[0] i2c serial data (sda), issp sdata*. b7 io i,m p0[2] analog column mux input. g7 io m p1[6] b8 io i,m p2[2] direct switched capacitor block input. g8 io m p3[4] b9 power vss ground connection. g9 io m p5[6] b10 power vss ground connection. g10 io p7[2] c1 nc no connection. h1 nc no connection. c2 io m p4[1] h2 io m p5[3] c3 io m p4[7] h3 io m p3[1] c4 io m p2[7] h4 io m p1[5] i2c serial data (sda). c5 io io,m p0[5] analog column mux input and column output. h5 io m p1[3] c6 io i,m p0[6] analog column mux input. h6 io m p1[2] c7 io i,m p0[0] analog column mux input. h7 io m p1[4] c8 io i,m p2[0] direct switched capacitor block input. h8 io m p3[2] c9 io m p4[2] h9 io m p5[4] c10 nc no connection. h10 io p7[3] d1 nc no connection. j1 power vss ground connection. d2 io m p3[7] j2 power vss ground connection. d3 io m p4[5] j3 usb d+ d4 io m p2[5] j4 usb d- d5 io io,m p0[3] analog column mux input and column output. j5 power vdd supply voltage. d6 io i,m p0[4] analog column mux input. j6 io p7[7] d7 io m p2[6] external voltage reference (vref) input. j7 io p7[0] d8 io m p4[6] j8 io m p5[2] d9 io m p4[0] j9 power vss ground connection. d10 cclk ocd cpu clock output. j10 power vss ground connection. e1 nc no connection. k1 power vss ground connection. e2 nc no connection. k2 power vss ground connection. e3 io m p4[3] k3 nc no connection. e4 io i,m p2[3] direct switched capacitor block input. k4 nc no connection. e5 power vss ground connection. k5 power vdd supply voltage. e6 power vss ground connection. k6 io p7[6] e7 io m p2[4] external analog ground (agnd) input. k7 io p7[5] e8 io m p4[4] k8 io p7[4] e9 io m p3[6] k9 power vss ground connection. e10 hclk ocd high-speed clock output. k10 power vss ground connection. legend a = analog, i = input, o = output, m = analog mux input, nc = no connection, ocd = on-chip debugger. * this is the issp pin, which is not high z at por. see the psoc mixed-signal array technical reference manual for details. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 16 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information cy8c24094 ocd not for production vss vss nc nc nc vdd nc nc vss vss vss vss p2[1] p0[1] p0[7] vdd p0[2] p2[2] vss vss nc p4[1] p4[7] p2[7] p0[5] p0[6] p0[0] p2[0] p4[2] nc nc p3[7] p4[5] p2[5] p0[3] p0[4] p2[6] p4[6] p4[0] cclk nc nc p4[3] p2[3] vss vss p2[4] p4[4] p3[6] hclk ocde p5[7] p3[5] p5[1] vss vss p5[0] p3[0] xres p7[1] ocdo p5[5] p3[3] p1[7] p1[1] p1[0] p1[6] p3[4] p5[6] p7[2] nc p5[3] p3[1] p1[5] p1[3] p1[2] p1[4] p3[2] p5[4] p7[3] vss vss d + d - vdd p7[7] p7[0] p5[2] vss vss vss vss nc nc vdd p7[6] p7[5] p7[4] vss vss 12345678910 a b c d e f g h j k bga (top view) [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 17 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information 1.7 100-pin part pinout (on-chip debug) the 100-pin tqfp part is for the cy 8c24094 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production. table 1-7. 100-pin part pinout (tqfp) pin no. digital analog name description pin no. digital analog name description 1 nc no connection. 51 io mp1[6] 2 nc no connection. 52 io mp5[0] 3 io i, m p0[1] analog column mux input. 53 io mp5[2] 4 io m p2[7] 54 io m p5[4] 5 io m p2[5] 55 io m p5[6] 6 io i, m p2[3] direct switched capacitor block input. 56 io mp3[0] 7 io i, m p2[1] direct switched capacitor block input. 57 io mp3[2] 8 io m p4[7] 58 io m p3[4] 9 io m p4[5] 59 io m p3[6] 10 io mp4[3] 60 hclk ocd high-speed clock output. 11 io mp4[1] 61 cclk ocd cpu clock output. 12 ocde ocd even data io. 62 input xres active high pin reset with internal pull down. 13 ocdo ocd odd data output. 63 io m p4[0] 14 nc no connection. 64 io mp4[2] 15 power vss ground connection. 65 power vss ground connection. 16 io m p3[7] 66 io m p4[4] 17 io m p3[5] 67 io m p4[6] 18 io mp3[3] 68 io i, m p2[0] direct switched capacitor block input. 19 io mp3[1] 69 io i, m p2[2] direct switched capacitor block input. 20 io m p5[7] 70 io p2[4] external analog ground (agnd) input. 21 io m p5[5] 71 nc no connection. 22 io mp5[3] 72 io p2[6] external voltage reference (vref) input. 23 io mp5[1] 73 nc no connection. 24 io m p1[7] i2c serial clock (scl). 74 io i p0[0] analog column mux input. 25 nc no connection. 75 nc no connection. 26 nc no connection. 76 nc no connection. 27 nc no connection. 77 io i, m p0[2] analog column mux input and column output. 28 io p1[5] i2c serial data (sda) 78 nc no connection. 29 io p1[3] 79 io i, m p0[4] analog column mux input and column output. 30 io p1[1] crystal (xtalin), i2c serial clock (scl), issp sclk*. 80 nc no connection. 31 nc no connection. 81 io i, m p0[6] analog column mux input. 32 power vss ground connection. 82 power vdd supply voltage. 33 usb d+ 83 nc no connection. 34 usb d- 84 power vss ground connection. 35 power vdd supply voltage. 85 nc no connection. 36 io p7[7] 86 nc no connection. 37 io p7[6] 87 nc no connection. 38 io p7[5] 88 nc no connection. 39 io p7[4] 89 nc no connection. 40 io p7[3] 90 nc no connection. 41 io p7[2] 91 nc no connection. 42 io p7[1] 92 nc no connection. 43 io p7[0] 93 nc no connection. 44 nc no connection. 94 nc no connection. 45 nc no connection. 95 io i, m p0[7] analog column mux input. 46 nc no connection. 96 nc no connection. 47 nc no connection. 97 io io, m p0[5] analog column mux input and column output. 48 io p1[0] crystal (xtalout), i2c serial data (sda), issp sdata*. 98 nc no connection. 49 io p1[2] 99 io io, m p0[3] analog column mux input and column output. 50 io p1[4] optional external clock input (extclk). 100 nc no connection. legend a = analog, i = input, o = output, nc = no connection, m = analog mux input, ocd = on-chip debugger. * these are the issp pins, which are not high z at por. see the psoc mixed-signal array technical reference manual for details. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 18 cy8c24094, cy8c24794, cy8c24894, and cy8c 24994 final data sheet 1. pin information cy8c24094 ocd not for production tqfp nc nc ai, m, p0[1] m, p2[7] m, p2[5] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] ocde ocdo nc vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, p1[7] nc nc d- p7[3] nc nc i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] nc vss d+ vdd p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] nc nc nc i2c sda, m, p1[0] m, p1[2] m, p1[4] nc p0[0], m, ai nc p2[6], m, external vref nc p2[4], m, external agnd p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m vss p4[2], m p4[0], m xres cclk hclk p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m nc p0[3], m, ai nc p0[5], m, ai nc p0[7], m, ai nc nc nc nc nc nc nc nc nc nc vss nc vdd p0[6], m, ai nc p0[4], m, ai nc p0[2], m, ai nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 19 2. register reference this chapter lists the registers of the cy8c24x94 psoc devi ce family. for detailed register information, reference the psoc mixed-signal array technical reference manual . 2.1 register conventions 2.1.1 abbreviations used the register conventions specific to this section are listed in the following table. 2.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 20 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet 2. register reference register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw pma0_dr 40 rw asc10cr0 80 rw c0 prt0ie 01 rw pma1_dr 41 rw asc10cr1 81 rw c1 prt0gs 02 rw pma2_dr 42 rw asc10cr2 82 rw c2 prt0dm2 03 rw pma3_dr 43 rw asc10cr3 83 rw c3 prt1dr 04 rw pma4_dr 44 rw asd11cr0 84 rw c4 prt1ie 05 rw pma5_dr 45 rw asd11cr1 85 rw c5 prt1gs 06 rw pma6_dr 46 rw asd11cr2 86 rw c6 prt1dm2 07 rw pma7_dr 47 rw asd11cr3 87 rw c7 prt2dr 08 rw usb_sof0 48 r 88 c8 prt2ie 09 rw usb_sof1 49 r 89 c9 prt2gs 0a rw usb_cr0 4a rw 8a ca prt2dm2 0b rw usbio_cr0 4b # 8b cb prt3dr 0c rw usbio_cr1 4c rw 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw ep1_cnt1 4e # 8e ce prt3dm2 0f rw ep1_cnt 4f rw 8f cf prt4dr 10 rw ep2_cnt1 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw ep2_cnt 51 rw asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw ep3_cnt1 52 # asd20cr2 92 rw d2 prt4dm2 13 rw ep3_cnt 53 rw asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw ep4_cnt1 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw ep4_cnt 55 rw asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw ep0_cr 56 # asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw ep0_cnt 57 # asc21cr3 97 rw i2c_scr d7 # 18 ep0_dr0 58 rw 98 i2c_dr d8 rw 19 ep0_dr1 59 rw 99 i2c_mscr d9 # 1a ep0_dr2 5a rw 9a int_clr0 da rw 1b ep0_dr3 5b rw 9b int_clr1 db rw prt7dr 1c rw ep0_dr4 5c rw 9c int_clr2 dc rw prt7ie 1d rw ep0_dr5 5d rw 9d int_clr3 dd rw prt7gs 1e rw ep0_dr6 5e rw 9e int_msk3 de rw prt7dm2 1f rw ep0_dr7 5f rw 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 21 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 final data sheet 2. register reference register map bank 1 tabl e: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw pma0_wa 40 rw asc10cr0 80 rw usbio_cr2 c0 rw prt0dm1 01 rw pma1_wa 41 rw asc10cr1 81 rw usb_cr1 c1 # prt0ic0 02 rw pma2_wa 42 rw asc10cr2 82 rw prt0ic1 03 rw pma3_wa 43 rw asc10cr3 83 rw prt1dm0 04 rw pma4_wa 44 rw asd11cr0 84 rw ep1_cr0 c4 # prt1dm1 05 rw pma5_wa 45 rw asd11cr1 85 rw ep2_cr0 c5 # prt1ic0 06 rw pma6_wa 46 rw asd11cr2 86 rw ep3_cr0 c6 # prt1ic1 07 rw pma7_wa 47 rw asd11cr3 87 rw ep4_cr0 c7 # prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw pma0_ra 50 rw 90 gdi_o_in d0 rw prt4dm1 11 rw pma1_ra 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw pma2_ra 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw pma3_ra 53 rw asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw pma4_ra 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw pma5_ra 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw pma6_ra 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw pma7_ra 57 rw asc21cr3 97 rw d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw prt7dm0 1c rw 5c 9c dc prt7dm1 1d rw 5d 9d osc_go_en dd rw prt7ic0 1e rw 5e 9e osc_cr4 de rw prt7ic1 1f rw 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw cmp_go_en1 65 rw a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcb03in 2d rw tmp_dr1 6d rw ad mux_cr5 ed rw dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 22 3. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c24x94 psoc device family. for the most up to date elec - trical specifications, c onfirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. specificat ions for devices running at greater than 12 mhz are valid for -40 o c t a 70 o c and t j 82 o c. figure 3-1. voltage versus cpu frequency the following table lists the units of measure that are used in this chapter. table 3-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa picoampere m ? megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l id o p e r a t i n g r e g i o n [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 23 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.1 absolute maximum ratings 3.2 operating temperature 3.3 dc electrical characteristics 3.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-2. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures will reduce data retention time. recommended storage temper- ature is +25 o c 25 o c. extended duration stor- age temperatures above 65 o c will degrade reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v io2 dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 3-3. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t ausb ambient temperature using usb -10 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedance? on page 42 . the user must limit the power con- sumption to comply with this requirement. table 3-4. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, tab l e 3 - 15 on page 29 . i dd5 supply current, imo = 24 mhz (5v) ? 14 27 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, ana- log power = off. i dd3 supply current, imo = 24 mhz (3.3v) ? 8 14 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, ana- log power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. a a. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled. ? 3 6.5 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, -40 o c t a 55 o c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. a ? 4 25 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, 55 o c < t a 85 o c, analog power = off. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 24 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.2 dc general purpose io specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.3.3 dc full-speed usb specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -10 c t a 85 c, or 3.0v to 3.6v and -10 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-5. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 200 ma maximum combined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. table 3-6. dc full-speed (12 mbps) usb specifications symbol description min typ max units notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) - (d-) | v cm differential input common mode range 0.8 ? 2.5 v v se single ended receiver threshold 0.8 ? 2.0 v c in transceiver capacitance ? ? 20 pf i io high-z state data line leakage -10 ? 10 a0v < v in < 3.3v. r ext external usb series resistor 23 ? 25 ? in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k ? 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 ? including r ext resistor. v crs d+/d- crossover voltage 1.3 ? 2.0 v [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 25 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.4 dc operational am plifier specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched capacitor psoc blocks. the guarantee d specifications are measured in the analog continuous time psoc block. table 3-7. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is mea- sured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ??db v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 26 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.5 dc low power comp arator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. table 3-8. 3.3v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ?? db v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd. table 3-9. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 27 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.6 dc analog output buffer specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-10. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? ? ? v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.1 0.5 x vdd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 x vdd - 1.3) v out (vdd - 2.3). table 3-11. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? ? ? v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 34 64 ? db (0.5 x vdd - 1.0) v out (0.5 x vdd + 0.9). [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 28 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.7 dc analog reference specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the guaranteed specific ations are measured through the an alog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 3-12. 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. vdd/2 - 0.04 vdd/2 - 0.01 vdd/2 + 0.007 v ? agnd = 2 x bandgap a 2 x bg - 0.048 2 x bg - 0.030 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) a p2[4] - 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap a bg - 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.022 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + bg - 0.10 vdd /2 + bg vdd /2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg - 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.113 2 x bg + p2[6] - 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6]+ 0.100 v ? refhi = 3.2 x bandgap 3.2 x bg - 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd /2 - bg - 0.04 vdd /2 - bg + 0.024 vdd /2 - bg + 0.04 v ? reflo = bandgap bg - 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 3-13. 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 a a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. vdd/2 - 0.03 vdd/2 - 0.01 vdd/2 + 0.005 v ? agnd = 2 x bandgap a not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap a bg - 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap a 1.6 x bg - 0.027 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = vdd/2) a -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.075 p2[4] + p2[6] - 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4]- p2[6] + 0.022 p2[4] - p2[6] + 0.092 v [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 29 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.8 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.3.9 dc por and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc mixed-signal array technical reference manual for more information on the vlt_cr register. table 3-14. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switched capacitor) ? 80 ? ff table 3-15. dc por and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 a 3.08 3.20 4.08 4.57 4.74 b 4.82 4.91 a. always greater than 50 mv above ppor (porlev = 00) for falling supply. b. always greater than 50 mv above ppor (porlev = 10) for falling supply. v v v v v v v v v [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 30 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.3.10 dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-16. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycl es each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.c ypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 31 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4 ac electrical characteristics 3.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-2. 24 mhz period jitter (imo) timing diagram table 3-17. ac chip-level specifications symbol description min typ max units notes f imo245v internal main oscillator frequency for 24 mhz (5v) 23.04 24 24.96 a,b mhz trimmed for 5v operation using factory trim values. f imo243v internal main oscillator frequency for 24 mhz (3.3v) 22.08 24 25.92 b,c mhz trimmed for 3.3v operation using factory trim values. f imousb5v internal main oscillator frequency with usb (5v) frequency locking enabled and usb traffic present. 23.94 24 24.06 b mhz -10 c t a 85 c 4.35 vdd 5.15 f imousb3v internal main oscillator frequency with usb (3.3v) frequency locking enabled and usb traffic present. 23.94 24 24.06 b mhz -0 c t a 70 c 3.15 vdd 3.45 f cpu1 cpu frequency (5v nominal) 0.93 24 24.96 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main osci llator with appropriate trim for vdd range. mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.96 b, c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting pso c microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. mhz f blk5 digital psoc block frequency (5v nominal) 0 48 49.92 a,b,d d. see the individual user module data sheets for in formation on maximum frequencies for user modules. mhz refer to the ac digital block specifications. f blk3 digital psoc block frequency (3.3v nominal) 0 24 25.92 b, d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz period jitter ? 100 ns step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.08 48.0 49.92 a,c mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) peak-to-peak ? 300 ps f max maximum frequency of signal on row input or row output. ? ? 12.96 mhz t ramp supply ramp time 0 ? ? s jitter24m1 f 24m [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 32 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.2 ac general purpose io specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-3. gpio timing diagram 3.4.3 ac full-speed usb specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -10 c t a 85 c, or 3.0v to 3.6v and -10 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-18. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 3-19. ac full-speed (12 mbps) usb specifications symbol description min typ max units notes t rfs transition rise time 4 ? 20 ns for 50 pf load. t fss transition fall time 4 ? 20 ns for 50 pf load. t rfmfs rise/fall time matching: (t r /t f )90 ? 111 % for 50 pf load. t dratefs full-speed data rate 12 - 0.25% 12 12 + 0.25% mbps tfallf tf alls trisef trises 90% 10% gpio pin output voltage [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 33 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.4 ac operational am plifier specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v . table 3-20. 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 3-21. 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 34 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies abov e the corner frequency defined by the on-chi p 8.1k resistance and the external capacit or. figure 3-4. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, po wer independent, and determined by device geometry. at high frequ en- cies, increased power level reduces the noise spectrum level. figure 3-5. typical opamp noise 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz ) dbv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 35 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.5 ac low power comp arator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. 3.4.6 ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 3.4.7 ac external clock specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-22. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 3-23. ac digital block specifications function description min typ max units notes timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the inpu t synchronizers running at 24 mhz (42 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 25.92 mhz counter enable pulse width 50 a ? ? ns maximum frequency, no enable input ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 25.92 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 a ? ? ns transmitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. table 3-24. ac external clock specifications symbol description min typ max units notes f oscext frequency for usb applications 23.94 24 24.06 mhz ? duty cycle 47 50 53 % ? power up to imo switch 150 ? ? s [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 36 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.8 ac analog output buffer specifications the following tables list guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-25. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 3-26. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 37 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.9 ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 3-27. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 38 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fi nal data sheet 3. electrical specifications 3.4.10 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and tem perature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 3-6. definition for timing for fast/standard mode on the i 2 c bus table 3-28. ac characteristics of the i 2 c sda and scl pins for vdd symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 39 4. packaging information this chapter illustrates the package spec ification for the cy8c24x94 psoc devices, along with the thermal impedance for the pac k- age and solder reflow peak temperatures. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.c om/design/mr10161 . 4.1 packaging dimensions figure 4-1. 56-lead (8x8 mm) qfn 001-12921 ** [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 40 cy8c24094, cy8c24794, cy8c24894, and cy8c249 94 final data sheet 4. packaging information figure 4-2. 68-lead (8x8 mm x 0.89 mm) qfn important note for information on the preferred dimensions for moun ting qfn packages, see the following application note at http://www.amkor.com /products/notes_pa pers/mlfappnote.pdf . important note pinned vias for thermal conduction are not required for the low-power psoc device. 51-85214 *c [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 41 cy8c24094, cy8c24794, cy8c24894, and cy8c249 94 final data sheet 4. packaging information figure 4-3. 100-ball (6x6 mm) vfbga figure 4-4. 100-lead (14x14 x 1.4 mm) tqfp 51-85209 *b 51-85048 *c [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 42 cy8c24094, cy8c24794, cy8c24894, and cy8c249 94 final data sheet 4. packaging information 4.2 thermal impedance 4.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 4-1. thermal impedance for the package package typical ja * 56 qfn** 12.93 o c/w 68 qfn** 13.05 o c/w 100 vfbga 65 o c/w * t j = t a + power x ja ** to achieve the thermal impedance specified for the qfn package, the center thermal pad should be soldered to the pcb ground plane. table 4-2. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 56 qfn 240 o c 260 o c 68 qfn 240 o c 260 o c 100 vfbga 240 o c 260 o c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 43 5. development tool selection this chapter presents the development tools available for all current psoc device families including the cy8c24x94 family. 5.1 software 5.1.1 psoc designer ? at the core of the psoc develo pment software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for half a decade. psoc designer is available free of charge at http:// www.cypress.com under design resources >> software and drivers. 5.1.2 psoc express ? as the newest addition to the psoc development software suite, psoc express is the first visual embedded system design tool that allows a user to create an entire psoc project and generate a schematic, bom, and data sheet without writing a single line of code. users work directly with application objects such as leds, switches, sensor s, and fans. psoc express is available free of charge at http://www.cypress.com/psocex- press . 5.1.3 psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programmi ng, psoc programmer works either as a standalone programming application or it can oper- ate directly from psoc desig ner or psoc express. psoc pro- grammer software is compatible with both psoc ice-cube in- circuit emulator and psoc miniprog. psoc programmer is available free ofcharge at http://www.cypress.com/psocpro- grammer. 5.1.4 cy3202-c imag ecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a cur- rent list of available items.. 5.2 development kits all development kits can be pu rchased from the cypress online store. 5.2.1 cy3215-dk basi c development kit the cy3215-dk is for protot yping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, ha lt, and single step the processor and view the content of specif ic memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 44 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fina l data sheet 5. development tool selection 5.2.2 cy3210-expressdk psoc express development kit the cy3210-expressdk is for adv anced prototyping and devel- opment with psoc express (may be used with ice-cube in-cir- cuit emulator). it provides access to i 2 c buses, voltage reference, switches, upgradeable modules and more. the kit includes: psoc express software cd express development board 4 fan modules 2 proto modules miniprog in-system serial programmer minieval pcb evaluation board jumper wire kit usb 2.0 cable serial cable (db9) 110 ~ 240v power supply, euro-plug adapter 2 cy8c24423a-24pxi 28-pdip chip samples 2 cy8c27443-24pxi 28-pdip chip samples 2 cy8c29466-24pxi 28-pdip chip samples 5.3 evaluation tools all evaluation tools can be purchased from the cypress online store. 5.3.1 cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programmi ng unit. the miniprog is a small, compact prototyping progra mmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable 5.3.2 cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable 5.3.3 cy3214-psocevalusb the cy3214-psocevalusb evalua tion kit features a develop- ment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunci- ator and plenty of bread boarding space to meet all of your eval- uation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack 5.4 device programmers all device programmers can be purchased from the cypress online store. 5.4.1 cy3216 modular programmer the cy3216 modular programmer kit features a modular pro- grammer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable 5.4.2 cy3207issp in -system serial programmer (issp) the cy3207issp is a production programmer . it includes pro- tection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compati- ble with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 45 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fina l data sheet 5. development tool selection 5.5 accessories (emulation and programming) 5.6 3rd-party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during develop- ment and production. s pecific details for each of these tools can be found at http://www.cypress.com under design resources >> evaluation boards. 5.7 build a psoc emulator into your board for details on how to emulate your circuit before going to vol- ume production using an on-chip debug (ocd) non-production psoc device, see application note ?debugging - build a psoc emulator into your board - an2323? at http://www.cypress.com/ an2323 . table 5-1. emulation and programming accessories part # pin package flex-pod kit a a. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. foot kit b b. foot kit includes surface mount feet th at can be soldered to the target pcb. adapter c c. programming adapter conv erts non-dip package to dip footprint. specific details and ordering information for each of the adapters can be found at http://www.emulation.com . cy8c24794 -24lfxi 56 qfn cy3250- 24x94qfn cy3250- 56qfn-fk as-56-28 cy8c24894 -24lfxi 56 qfn cy3250- 24x94qfn cy3250- 56qfn-fk as-28-28-02ss- 6eng-gang [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 46 6. ordering information the following table lists the cy8c24x94 psoc device?s key package features and ordering codes. 6.1 ordering code definitions table 6-1. cy8c24x94 psoc device?s key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital io pins analog inputs analog outputs xres pin 56 pin (8x8 mm) qfn cy8c24794-24lfxi 16k 1k -40c to +85c 4 6 50 48 2 no 56 pin (8x8 mm) qfn (tape and reel) cy8c24794-24lfxit 16k 1k -40c to +85c 4 6 50 48 2 no 56 pin (8x8 mm) qfn cy8c24894-24lfxi 16k 1k -40c to +85c 4 6 49 47 2 yes 56 pin (8x8 mm) qfn (tape and reel) cy8c24894-24lfxit 16k 1k -40c to +85c 4 6 49 47 2 yes 68 pin ocd (8x8 mm) qfn a a. this part may be used for in-circuit debugging. it is not available for production. cy8c24094-24lfxi 16k 1k -40c to +85c 4 6 56 48 2 yes 68 pin (8x8 mm) qfn CY8C24994-24lfxi 16k 1k -40c to +85c 4 6 56 48 2 yes 68 pin (8x8 mm) qfn (tape and reel) CY8C24994-24lfxit 16k 1k -40c to +85c 4 6 56 48 2 yes 100 ball ocd (6x6 mm) vfbga a cy8c24094-24bvxi 16k 1k -40c to +85c 4 6 56 48 2 yes 100 ball (6x6 mm) vfbga CY8C24994-24bvxi 16k 1k -40c to +85c 4 6 56 48 2 yes 100 pin ocd tqfp a cy8c24094-24axi 16k 1k -40c to +85c 4 6 56 48 2 yes cy 8 c 24 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx = qfn pb-free ax = tqfp pb-free bvx = vfbga pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback [+] feedback
february 15, 2007 ? cypress semiconductor 2004-2007 ? document no. 38-12018 rev. *j 47 7. sales and company information to obtain information about cypress semiconductor or psoc sa les and technical support, reference the following information. cypress semiconductor 7.1 revision history 198 champion court san jose, ca 95134 408.943.2600 web sites: company information ? http://www.cypress.com sales ? http://www.cypress. com/aboutus/sale s_locations.cfm technical support ? http://www.cypress.com/support/login.cfm table 6-1. cy8c24x94 data sheet revision history document title: cy8c24094, cy8c24794, cy8c24894 and CY8C24994 psoc? mixed-signal array final data sheet document number: 38-12018 revision ecn # issue date origin of change description of change ** 133189 01.27.2004 nwj new silicon and new document ? advance data sheet. *a 251672 see ecn sfv first preliminary data sheet. changed title to encompass only the cy8c24794 because the cy8c24494 and cy8c24694 are not being offered by cypress microsystems. *b 289742 see ecn hmt add standard ds items from sfv memo. add analog input mux on pinouts. 2 macs. change 512 bytes of sram to 1k. add dimension key to package. remo ve hapi. update diagrams, registers and specs. *c 335236 see ecn hmt add cy logo. update cy copyright. update new cy.com urls. re-add issp programming pinout notation. add reflow temp. table. update features (mac, osc illator, and voltage range), registers (int_clr2/msk2, second mac), and specs. (rext, imo, analog output buffer...). *d 344318 see ecn hmt add new color and logo. expand analog arch. diagram. fix io #. update electrical specifications. *e 346774 see ecn hmt add usb temperature specifications. make data sheet final. *f 349566 see ecn hmt remove usb logo. add url to preferred dimensions for mounting mlf packages. *g 393164 see ecn hmt add new device, cy8c24894 56-pin mlf with xres pin. add fimousb3v char. to specs. upgrade to cy per- form logo and update corporate address and copyright. *h 469243 see ecn hmt add issp note to pinout tables. update typical and recommended storage temperature per industrial specs. update low output level maximum iol budget. add fls_ pr1 to register map bank 1 for users to specify which flash bank should be used for srom operations . add two new devices for a 68-pin qfn and 100-ball vfbga under rpns: cy8c24094 and CY8C24994. add two packages for 68-pin qfn. add ocd non-produc- tion pinouts and package diagrams. update cy branding and qfn convention. add new dev. tool section. update copyright and trademarks. *i 561158 see ecn hmt add low power comparator (lpc) ac/dc electrical sp ec. tables. add cy8c20x34 to psoc device character- istics table. add detailed dimensions to 56-pin qfn pa ckage diagram and update revision. secure one package diagram/manufacturing per qfn. update emulation pod/feet kit part numbers. fix pin out type-o per testtrack. *j 728238 see ecn hmt add capsense snr requirement reference. update figure standards. update technical training paragraphs. add qfn package clarifications and dimensions. upda te ecn-ed amkor dimensioned qfn package diagram revisions. reword snr reference. add new 56-pin qfn spec. distribution : external/public posting : none [+] feedback [+] feedback
february 15, 2007 document no. 38-12018 rev. *j 48 cy8c24094, cy8c24794, cy8c24894, and CY8C24994 fina l data sheet 7. sales and company information 7.2 copyrights and code protection ? cypress semiconductor corporation. 2004-2007. all rights reserv ed. psoc designer?, programmable system-on-chip?, and psoc exp ress? are trademarks and psoc? is a registered trademark of cypress semiconductor corp. a ll other trademarks or registered trademarks referenced herein are property of the respective corpo- rations. the information contained herein is subject to change without notice. cypress semicondu ctor assumes no responsibility for the u se of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license under patent or other rights. cypress semi conductor does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonabl y be expected to result in s ignificant injury to the user. the inclusion of cypress semiconductor products in life-suppor t systems application implies that the manufa cturer assumes all risk of such use a nd in doing so indemnifies cypress semiconductor against all charges. cypress semiconductor products are not warranted nor intended to be used for medical, life-s upport, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress semiconductor. note the following details of the flash code protecti on features on cypress semiconductor psoc devices. cypress semiconductor products meet the spec ifications contained in their particular cypress semiconductor data sheets. cypress semiconductor believes that its fam- ily of products is one of the most secure fa milies of its kind on the market today, re gardless of how they are used. there may be methods, unknown to cypress semicon- ductor, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly i llegal. neither cypress semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are gu aranteeing the product as "unbreak- able." cypress semiconductor is willing to work with the custom er who is concerned about the integrity of their code. code prot ection is constantly evolving. we at cypress semiconductor are committed to continuously im proving the code protection features of our products. [+] feedback [+] feedback

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